Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell
نویسندگان
چکیده
منابع مشابه
Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell
This paper describes a soft-error tolerant and marginenhanced nMOS-pMOS reversed 6T SRAM cell. The 6T SRAM bitcell comprises pMOS access and driver transistors, and nMOS load transistors. Therefore, the nMOS and pMOS masks are reversed in comparison with those of a conventional bitcell. In scaled process technology, The pMOS transistors present advantages of small random dopant fluctuation, str...
متن کاملBit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read ope...
متن کاملComparison of Conventional 6T SRAM cell and FinFET based 6T SRAM Cell Parameters at 45nm Technology
When working for low power application the main estimation is to reduce leakage components and parameters. This stanza explores a vast link towards low leakage power SRAM cells using new technology and devices. The RAM contains bi-stable cross coupled latch which has V_th higher in write mode access MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and lower V_th in read access mode MO...
متن کاملImpact of circuit assist methods on margin and performance in 6T SRAM
0038-1101/$ see front matter 2010 Elsevier Ltd. A doi:10.1016/j.sse.2010.06.009 * Corresponding author. E-mail addresses: [email protected] (R.W. Ma Wang), [email protected] (S. Nalam), sk4fs@virgin us.ibm.com (G. Braceras), [email protected] (H. Pilo) Calhoun). Large scale 6T SRAM beyond 65 nm will increasingly rely on assist methods to overcome the functional limitations associated with scal...
متن کاملStatic Write Margin and Power for 6T & 7T SRAM Cell: A Comparison
SRAM cell read stability and write-ability are major concerns in CMOS technologies, due to the progressive increase in VDD and transistor scaling. In this paper, we studied and comparedthe performance of 7TN (with NMOS access transistor), 7TP (with PMOS access transistor) andconventional 6T structure.SRAM cells have been simulated in SPICE with 0.35 μm technology. The techniques that provide th...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
سال: 2014
ISSN: 0916-8508,1745-1337
DOI: 10.1587/transfun.e97.a.1945